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? semiconductor components industries, llc, 2011 may, 2011 ? rev. 8 1 publication order number: mc74lvx4053/d mc74lvx4053 analog multiplexer/ demultiplexer high ? performance silicon ? gate cmos the mc74lvx4053 utilizes silicon ? gate cmos technology to achieve fast propagation delays, low on resistances, and low off leakage currents. this analog multiplexer/demultiplexer controls analog voltages that may vary across the complete power supply range (from v cc to v ee ). the lvx4053 is similar in pinout to the lvx8053, the hc4053a, and the metal ? gate mc14053b. the channel ? select inputs determine which one of the analog inputs/outputs is to be connected, by means of an analog switch, to the common output/input. when the enable pin is high, all analog switches are turned off. the channel ? select and enable inputs are compatible with standard cmos outputs; with pullup resistors, they are compatible with lsttl outputs. this device has been designed so the on resistance (r on ) is more linear over input voltage than the r on of metal ? gate cmos analog switches and high ? speed cmos analog switches. features ? fast switching and propagation speeds ? low crosstalk between switches ? analog power supply range (v cc ? v ee ) = 3.0 v to 3.0 v ? digital (control) power supply range (v cc ? gnd) = 2.5 to 6.0 v ? improved linearity and lower on resistance than metal ? gate, hsl, or vhc counterparts ? low noise ? designed to operate on a single supply with v ee = gnd, or using split supplies up to 3.0 v ? break ? before ? make circuitry ? these devices are pb ? free and are rohs compliant figure 1. pin connection and marking diagram (top view) 15 16 14 13 12 11 10 2 1 34567 v cc 9 8 y x x1 x0 a b c y1 y0 z1 z z0 enable v ee gnd http://onsemi.com see detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet. ordering information marking diagrams tssop ? 16 dt suffix case 948f soeiaj ? 16 m suffix case 966 soic ? 16 d suffix case 751b lvx4053g awlyww lvx4053 alywg 1 16 1 16 1 16 lvx4053 = specific device code a = assembly location wl, l = wafer lot y = year ww, w = work week g or = pb ? free package (note: microdot may be in either location) lvx 4053 alyw
mc74lvx4053 http://onsemi.com 2 x = don?t care figure 2. logic diagram triple single ? pole, double ? position plus common off l l l l h h h h x l l h h l l h h x l h l h l h l h x function table control inputs on channels enable select cba l l l l l l l l h z0 z0 z0 z0 z1 z1 z1 z1 y0 y0 y1 y1 y0 y0 y1 y1 x0 x1 x0 x1 x0 x1 x0 x1 none x0 12 x1 13 a 11 b 10 c 9 enable 6 x switch y switch x 14 analog inputs/outputs channel\select inputs pin 16 = v cc pin 8 = gnd pin 7 = v ee common outputs/inputs y0 2 y1 1 y 15 z0 5 z1 3 z 4 z switch note: this device allows independent control of each switch. channel ? select input a controls the x ? switch, input b controls the y ? switch and input c controls the z ? switch ordering information device package shipping ? MC74LVX4053DG soic ? 16 (pb ? free) 48 units / rail mc74lvx4053dr2g soic ? 16 (pb ? free) 2500 tape & reel mc74lvx4053dtg tssop ? 16* 96 units / rail mc74lvx4053dtr2g tssop ? 16* 2500 tape & reel mc74lvx4053mg soeiaj ? 16 (pb ? free) 50 units / rail mc74lvx4053melg soeiaj ? 16 (pb ? free) 2000 tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d. *this package is inherently pb ? free.
mc74lvx4053 http://onsemi.com 3 ????????????????????????????????? ????????????????????????????????? ????? ????? ????????????????????? ????????????????????? ??????? ??????? ??? ??? ????? ????? v ee ????????????????????? ????????????????????? ??????? ??????? 7.0 to 0.5 ??? ??? ????? ????? ????????????????????? ????????????????????? ??????? ??????? 0.5 to 7.0 0.5 to 7.0 ??? ??? ????? ????? ????????????????????? ????????????????????? ??????? ??????? 0.5 to v cc 0.5 ??? ??? ????? ????? ????????????????????? ????????????????????? ??????? ??????? 0.5 to 7.0 ??? ??? ????? ????? ????????????????????? ????????????????????? ??????? ??????? 20 ??? ??? ????? ????? ????????????????????? ????????????????????? ??????? ??????? 65 to 150 ??? ??? c ????? ????? ????????????????????? ????????????????????? ??????? ??????? ??? ??? c ????? ????? ????????????????????? ????????????????????? ??????? ??????? 150 ??? ??? c ????? ????? ????? ja ????????????????????? ????????????????????? ????????????????????? ??????? ??????? ??????? ??? ??? ??? c/w ????? ????? ????? ????????????????????? ????????????????????? ????????????????????? ??????? ??????? ??????? ??? ??? ??? ????? ????? ????????????????????? ????????????????????? ??????? ??????? ??? ??? ????? ????? ????????????????????? ????????????????????? ? 35% ??????? ??????? ? 94 ? vo (0.125 in) ??? ??? ????? ????? ????? ????????????????????? ????????????????????? ????????????????????? ??????? ??????? ??????? 2000 200 1000 ??? ??? ??? ????? ????? ????????????????????? ????????????????????? c (note 4) ??????? ??????? 300 ??? ??? ? a114 ? a. 2. tested to eia/jesd22 ? a115 ? a. 3. tested to jesd22 ? c101 ? a. 4. tested to eia/jesd78. recommended operating conditions symbol parameter min max unit ????? ????? v ee ????????????????????? ????????????????????? ???? ???? 6.0 ???? ???? ??? ??? ????? ????? ????????????????????? ????????????????????? ???? ???? ???? ???? ??? ??? ????? ????? ????????????????????? ????????????????????? ???? ???? ???? ???? ??? ??? ????? ????? ????????????????????? ????????????????????? ???? ???? ???? ???? ??? ??? ????? ????? ????????????????????? ????????????????????? ???? ???? 55 ???? ???? ??? ??? c ????? ????? ????? ????????????????????? ????????????????????? ????????????????????? 0.3 v (channel select or enable inputs) v cc = 5.0 v 0.5 v ???? ???? ???? ???? ???? ???? ??? ??? ??? ? logic voltage level or a low ? logic input voltage level. device junction temperature versus time to 0.1% bond failures junction temperature c time, hours time, years 80 1,032,200 117.8 90 419,300 47.9 100 178,700 20.4 110 79,600 9.4 120 37,000 4.2 130 17,800 2.0 140 8,900 1.0 1 1 10 100 1000 failure rate of plastic = ceramic until intermetallics occur figure 3. failure rate vs. time junction temperature normalized failure rate time, years t j = 130 c t j = 120 c t j = 110 c t j = 100 c t j = 90 c t j = 80 c
mc74lvx4053 http://onsemi.com 4 dc characteristics ? digital section (voltages referenced to gnd) symbol parameter condition v cc v guaranteed limit unit 55 to 25 c 85 c 125 c v ih minimum high ? level input voltage, channel ? select or en- able inputs 2.5 3.0 4.5 6.0 1.90 2.10 3.15 4.2 1.90 2.10 3.15 4.2 1.90 2.10 3.15 4.2 v v il maximum low ? level input voltage, channel ? select or en- able inputs 2.5 3.0 4.5 6.0 0.6 0.9 1.35 1.8 0.6 0.9 1.35 1.8 0.6 0.9 1.35 1.8 v i in maximum input leakage current, channel ? select or en- able inputs v in = 6.0 or gnd 0 v to 6.0 v 0.1 1.0 1.0 a i cc maximum quiescent supply current (per package) channel select, enable and v is = v cc or gnd 6.0 4.0 40 80 a dc electrical characteristics ? analog section ???? ???? ???? ????????? ????????? ????????? ??????? ??????? ??????? ??? ??? ??? ??? ??? ??? ??????????? ??????????? ?? ?? ?? ?????? ?????? 55 to 25 c ??? ??? 85 c ???? ???? 125 c ???? ???? ???? ???? r on ????????? ????????? ????????? ????????? ??????? ??????? ??????? ??????? ? (v cc ? v ee ) |i s | = 2.0 ma (figure 4) ??? ??? ??? ??? ??? ??? ??? ??? 3.0 ?????? ?????? ?????? ?????? ??? ??? ??? ??? ???? ???? ???? ???? ?? ?? ?? ?? ???? ???? ???? ???? r on ????????? ????????? ????????? ????????? ??????? ??????? ??????? ??????? ? (v cc ? v ee ) |i s | = 2.0 ma ??? ??? ??? ??? ??? ??? ??? ??? 3.0 ?????? ?????? ?????? ?????? ??? ??? ??? ??? ???? ???? ???? ???? ?? ?? ?? ?? i off maximum off ? channel leakage current, any one channel v in = v il or v ih ; v io = v cc or gnd; switch off (figure 3) 5.5 +3.0 0 ? 3.0 0.1 0.1 0.5 0.5 1.0 1.0 a maximum off ? channel leakage current, common channel v in = v il or v ih ; v io = v cc or gnd; switch off (figure 4) 5.5 +3.0 0 ? 3.0 0.2 0.2 2.0 2.0 4.0 4.0 i on maximum on ? channel leakage current, channel ? to ? channel v in = v il or v ih ; switch ? to ? switch = v cc or gnd; (figure 5) 5.5 +3.0 0 ? 3.0 0.2 0.2 2.0 2.0 4.0 4.0 a ac characteristics (input t r = t f = 3 ns) ???? ???? ???? ???? symbol ????????? ????????? ????????? ????????? ??????? ??????? ??????? ??????? ??? ??? ??? ??? ??? ??? ??? ??? ??????????? ??????????? ?? ?? ?? ?? ?????? ?????? 55 to 25 c ??? ??? ??? 85 c ???? ???? ???? 125 c ??? ??? ???? ???? t bbm min. break ? before ? make time v in = v il or v ih v is = v cc r l = 300 c l = 35 pf (figures 12 and 13) 3.0 4.5 3.0 0.0 0.0 3.0 1.0 1.0 1.0 6.5 5.0 3.5 ? ? ? ? ? ? ns *typical characteristics are at 25 c.
mc74lvx4053 http://onsemi.com 5 ac characteristics (c l = 50 pf, input t r = t f = 3 ns) symbol parameter v cc v v ee v guaranteed limit unit 55 to 25 c 85 c 125 c min typ max min max min max t plh , t phl maximum propagation delay, channel ? select to analog output (figures 16 and 17) 2.5 3.0 4.5 3.0 0 0 0 3.0 40 28 23 23 45 30 25 25 50 35 30 28 ns t plz , t phz maximum propagation delay, enable to analog output (figures 14 and 15) 2.5 3.0 4.5 3.0 0 0 0 3.0 40 28 23 23 45 30 25 25 50 35 30 28 ns t pzl , t pzh maximum propagation delay, enable to analog output (figures 14 and 15) 2.5 3.0 4.5 3.0 0 0 0 3.0 40 28 23 23 45 30 25 25 50 35 30 28 ns c pd power dissipation capacitance (figure 18) (note 6) typical @ 25 c, v cc = 5.0 v, v ee = 0v 45 pf c in maximum input capacitance, channel ? select or enable inputs 10 pf c i/o maximum capacitance analog i/o (all switches off) common o/i feedthrough 10 10 1.0 pf 6. used to determine the no ? load dynamic power consumption: p d = c pd v cc 2 f + i cc v cc . additional application characteristics (gnd = 0 v) symbol parameter condition v cc v v ee v typ unit 25 c bw maximum on ? channel bandwidth or minimum frequency response v is = ? (v cc ? v ee ) ref and test attn = 10 db source amplitude = 0 db (figure 7) 3.0 4.5 6.0 3.0 0.0 0.0 0.0 3.0 80 80 80 80 mhz v iso off ? channel feedthrough isolation f = 1 mhz; v is = ? (v cc ? v ee ) adjust network analyzer output to 10 dbm on each output from the power splitter (figures 8 and 9) 3.0 4.5 6.0 3.0 0.0 0.0 0.0 3.0 70 70 70 70 db v onl maximum feedthrough on loss v is = ? (v cc ? v ee ) adjust network analyzer output to 10 dbm on each output from the power splitter (figure 11) 3.0 4.5 6.0 3.0 0.0 0.0 0.0 3.0 2 2 2 2 db q charge injection v in = v cc to v ee, f is = 1 khz, t r = t f = 3 ns r is = 0 , c l = 1000 pf, q = c l * v out (figure 10) 5.0 3.0 0.0 3.0 9.0 12 pc thd total harmonic distortion thd + noise f is = 1 mhz, r l = 10 k , c l = 50 pf, v is = 5.0 v pp sine wave v is = 6.0 v pp sine wave (figure 19) 6.0 3.0 0.0 3.0 0.10 0.05 %
mc74lvx4053 http://onsemi.com 6 figure 4. on resistance, test set ? up plotter mini computer programmable power supply dc analyzer v cc device under test gnd analog in common out gnd figure 5. maximum off channel leakage current, any one channel, test set ? up figure 6. maximum on channel leakage current, channel to channel, test set ? up figure 7. maximum on channel bandwidth, test set ? up off off 6 7 8 16 common o/i v cc v ih nc a v cc v ee v cc on off 6 7 8 16 common o/i v cc v il v cc v ee v cc n/c a analog i/o v ee v ee on off 6 7 8 v cc v ee 9 ? 11 all untested analog i/o pins hp11667b pwr splitter hp4195a network anl 0.1 f s1 r1 t1 0.1 f 50 k 100 k v is a channel selects connected to address pins on hp4195a and appropriately configured to test each switch.
mc74lvx4053 http://onsemi.com 7 figure 8. maximum off channel feedthrough isolation, test set ? up figure 9. maximum common ? channel feedthrough isolation, test set ? up off on 6 7 8 v cc v ee 9 ? 11 all untested analog i/o pins hp11667b pwr splitter hp4195a network anl 0.1 f s1 r1 t1 0.1 f 50 k 100 k v is 16 config = network format = t/r (db) cal = trans cal display = rectan x a b scale ref = auto scale view = off, off, off trig = cont mode source amplitude = 13 db reference attenuation = 20 db test attenuation = 0 db v iso (db) = 20 log (v t1 /v r1 ) 6 7 8 v cc v ee 9 ? 11 all untested analog i/o pins hp11667b pwr splitter hp4195a network anl 0.1 f s1 r1 t1 0.1 f 50 100 k v is 16 config = network format = t/r (db) cal = trans cal display = rectan x a b scale ref = auto scale view = off, off, off trig = cont mode source amplitude = 13 db reference attenuation = 20 db test attenuation = 0 db v isoc (db) = 20 log (v t1 /v r1 ) on 50 k off channel selects connected to address pins on hp4195a and appropriately configured to test each switch. channel selects connected to address pins on hp4195a and appropriately configured to test each switch.
mc74lvx4053 http://onsemi.com 8 figure 10. charge injection, test set ? up on/off 7 8 v cc v out off/on 9 ? 11 c l * v ih v il *includes all probe and jig capacitance. 16 bias channel selects to test each combination of analog inputs to common analog output. 6 enable v ee v in r is v is v out v out q = c l * v out figure 11. maximum on channel feedthrough on loss, test set ? up off on 6 7 8 v cc v ee 9 ? 11 all untested analog i/o pins hp11667b pwr splitter hp4195a network anl 0.1 f s1 r1 t1 0.1 f 50 100 k v is 16 config = network format = t/r (db) cal = trans cal display = rectan x a b scale ref = auto scale view = off, off, off trig = cont mode source amplitude = 13 db reference attenuation = 20 db test attenuation = 20 db v onl (db) = 20 log (v t1 /v r1 ) channel selects connected to address pins on hp4195a and appropriately configured to test each switch.
mc74lvx4053 http://onsemi.com 9 figure 12. break ? before ? make, test set ? up figure 13. break ? before ? make time on off 6 7 8 v cc v ee 9 ? 11 tek 11801b dso com input 16 r l c l v in 50 v in 80% v cc t bbm 80% of v oh figure 14. propagation delays, channel select to analog out figure 15. propagation delay, test set ? up channel select to analog out v cc gnd channel select analog out 50% t plh t phl 50% on/off 6 7 8 16 v cc c l * channel select test point common off/on analog i/o v cc on/off 6 7 8 enable v cc enable 90% 50% 10% t f t r v cc gnd analog out t pzl analog out t pzh high impedance v ol v oh high impedance 10% 90% t plz t phz 50% 50% analog i/o c l * test point 16 v cc 1 k 1 2 1 2 position 1 when testing t phz and t pzh position 2 when testing t plz and t pzl gnd gnd o/i channel selects connected to v in and appropriately configured to test each switch. v oh *includes all probe and jig capacitance. figure 16. propagation delays, enable to analog out figure 17. propagation delay, test set ? up enable to analog out
mc74lvx4053 http://onsemi.com 10 figure 18. power dissipation capacitance, test set ? up on/off 12 v cc nc off/on 10 ? 11, 13 ? 14 channel select 15 v il v cc a figure 19. total harmonic distortion, test set ? up 6 7 8 9 ? 11 hp3466 dmm 16 50 k v com hp3466 dmm v com hp e3630a dc pwr supply com 20 v 20 v hp 339 distortion measurement set analyzer input com oscillator output com r l c l on off channel selects connected to dc bias supply or ground and appropriately configured to test each switch.
mc74lvx4053 http://onsemi.com 11 applications information the channel select and enable control pins should be at v cc or gnd logic levels. v cc being recognized as a logic high and gnd being recognized as a logic low. in this example: v cc = 5 v = logic high gnd = 0 v = logic low the maximum analog voltage swing is determined by the supply voltages v cc and v ee . the positive peak analog voltage should not exceed v cc . similarly, the negative peak analog voltage should not go below v ee . in this example, the difference between v cc and v ee is 5.0 volts. therefore, using the configuration of figure 21, a maximum analog signal of 5.0 volts peak ? to ? peak can be controlled. unused analog inputs/outputs may be left floating (i.e., not connected). however, tying unused analog inputs and outputs to v cc or gnd through a low value resistor helps minimize crosstalk and feedthrough noise that may be picked up by an unused switch. although used here, balanced supplies are not a requirement. the only constraints on the power supplies are that: v ee ? gnd = 0 to 6 volts v cc ? gnd = 2.5 to 6 volts v cc ? v ee = 2.5 to 6 volts and v ee gnd when voltage transients above v cc and/or below v ee are anticipated on the analog channels, external germanium or schottky diodes (d x ) are recommended as shown in figure 22. these diodes should be able to absorb the maximum anticipated current surges during clipping. analog signal figure 20. application example on 6 7 8 16 +3.0 v analog signal +3.0 v ? 3.0 v +3.0 v ? 3.0 v 11 10 9 to external cmos circuitry 0 to 3.0 v digital signals ? 3.0 v figure 21. application example analog signal on 6 7 8 16 +5 v analog signal +5 v gnd +5 v gnd 11 10 9 to external cmos circuitry 0 to 5 v digital signals on/off 7 8 16 v cc v ee d x v cc d x v ee d x v cc d x v ee figure 22. external germanium or schottky clipping diodes
mc74lvx4053 http://onsemi.com 12 figure 23. function diagram, lvx4053 13 x1 12 x0 1 y1 2 y0 3 z1 5 z0 14 x level shifter level shifter level shifter level shifter 11 a 10 b 9 c 6 enable 15 y 4 z
mc74lvx4053 http://onsemi.com 13 package dimensions soic ? 16 d suffix case 751b ? 05 issue k *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 6.40 16x 0.58 16x 1.12 1.27 dimensions: millimeters 1 pitch 16 89 8x notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 18 16 9 seating plane f j m r x 45 g 8 pl p ? b ? ? a ? m 0.25 (0.010) b s ? t ? d k c 16 pl s b m 0.25 (0.010) a s t dim min max min max inches millimeters a 9.80 10.00 0.386 0.393 b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.054 0.068 d 0.35 0.49 0.014 0.019 f 0.40 1.25 0.016 0.049 g 1.27 bsc 0.050 bsc j 0.19 0.25 0.008 0.009 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 5.80 6.20 0.229 0.244 r 0.25 0.50 0.010 0.019
mc74lvx4053 http://onsemi.com 14 package dimensions tssop ? 16 dt suffix case 948f ? 01 issue b *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 7.06 16x 0.36 16x 1.26 0.65 dimensions: millimeters 1 pitch ??? ??? dim min max min max inches millimeters a 4.90 5.10 0.193 0.200 b 4.30 4.50 0.169 0.177 c ??? 1.20 ??? 0.047 d 0.05 0.15 0.002 0.006 f 0.50 0.75 0.020 0.030 g 0.65 bsc 0.026 bsc h 0.18 0.28 0.007 0.011 j 0.09 0.20 0.004 0.008 j1 0.09 0.16 0.004 0.006 k 0.19 0.30 0.007 0.012 k1 0.19 0.25 0.007 0.010 l 6.40 bsc 0.252 bsc m 0 8 0 8 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a does not include mold flash. protrusions or gate burrs. mold flash or gate burrs shall not exceed 0.15 (0.006) per side. 4. dimension b does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 (0.010) per side. 5. dimension k does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the k dimension at maximum material condition. 6. terminal numbers are shown for reference only. 7. dimension a and b are to be determined at datum plane ? w ? . section n ? n seating plane ident. pin 1 1 8 16 9 detail e j j1 b c d a k k1 h g ? u ? s u 0.15 (0.006) t s u 0.15 (0.006) t s u m 0.10 (0.004) v s t 0.10 (0.004) ? t ? ? v ? ? w ? 0.25 (0.010) 16x ref k n n
mc74lvx4053 http://onsemi.com 15 package dimensions soeiaj ? 16 m suffix case 966 ? 01 issue a h e a 1 dim min max min max inches --- 2.05 --- 0.081 millimeters 0.05 0.20 0.002 0.008 0.35 0.50 0.014 0.020 0.10 0.20 0.007 0.011 9.90 10.50 0.390 0.413 5.10 5.45 0.201 0.215 1.27 bsc 0.050 bsc 7.40 8.20 0.291 0.323 0.50 0.85 0.020 0.033 1.10 1.50 0.043 0.059 0 0.70 0.90 0.028 0.035 --- 0.78 --- 0.031 a 1 h e q 1 l e 10 0 10 l e q 1 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions d and e do not include mold flash or protrusions and are measured at the parting line. mold flash or protrusions shall not exceed 0.15 (0.006) per side. 4. terminal numbers are shown for reference only. 5. the lead width dimension (b) does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the lead width dimension at maximum material condition. dambar cannot be located on the lower radius or the foot. minimum space between protrusions and adjacent lead to be 0.46 ( 0.018). m l detail p view p c a b e m 0.13 (0.005) 0.10 (0.004) 1 16 9 8 d z e a b c d e e l m z on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. mc74lvx4053/d publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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